In some situations it is necessary to multiply the frequency of an input signal, e.g., an input clock signal. As described below, a case in point is a data separator which includes a digital phase-locked loop.
In digital communications systems, binary numbers are electronically represented by high and low voltage signals, transmitted through a single wire. For successful error-free communication, a receiver must extract both data and clock signals from the single-bit stream, and then sample the data using the extracted clock signal. To accomplish this, a phase-locked loop (PLL) is normally used to regenerate the desired clock signal and synchronize it with the received data bit stream. Data separators are used, for example, in controllers for floppy disk drives, where they synchronize a stream of data bits which are read from a magnetic storage disk.
Most conventional data separators use analog PLLs to generate the sampling clock signal. Analog PLLs have the potential of infinite resolution, but they require precise components, such as resistors and capacitors, either external or internal. These components are susceptible to variations in the manufacturing process. Furthermore, analog PLLs are susceptible to signal noise, which also limits their resolution in practical terms.
To avoid these disadvantages, digital PLLs have been developed. Digital PLL circuits do not require precision components. However, the resolution of a digital PLL circuit is limited to its effective sampling interval, which is the minimum interval at which samples may be taken. In order to increase the resolution of a digital PLL, a high-speed clock signal increments a counter to a preselected number, and the counter supplies sample clock pulses to a comparator for comparison with the received clock signal. For CMOS circuits, the sample clock signal must be relatively high (e.g., 100 MHz). In a digital PLL, the frequency of the high-speed clock signal is usually divided by an integer number, and the resulting clock signal is compared with the clock field of the received data signal.
The high-speed clock signal may be provided by an external source, an internal free-running oscillator, an internal voltage-controlled oscillator, or an internal digital-controlled oscillator. In the latter case, the digital-controlled oscillator is included in a digital frequency multiplier that is supplied with a relatively slow reference clock. Economically, it is normally preferable to frequency multiply an available slow clock signal rather than to use an external high-speed clock signal directly.
Prior art data separators utilizing digital-controlled oscillators have suffered from accuracy and stability problems. These problems are greatly reduced using the frequency multiplier of this invention.